1. Technical Field
The present invention relates to a semiconductor device.
2. Related Art
In the past, in a manufacturing procedure of semiconductor chips, testing of circuit portions may be performed in a state where a plurality of semiconductor chip circuit portions is formed over semiconductor wafers.
At this time, a method of performing the testing of the circuit portions through communication with external devices in a non-contact manner is proposed (see, for example, Japanese Laid-Open Patent Publication NO. 2005-30877).
When such testing is performed, it is difficult to perform even the supplying of power or grounding in a non-contact manner. For this reason, pads connected to the circuit portions respectively are formed, power is supplied by probing on these pads, or grounding is performed by probing on these pads. Even though communication with the external devices is performed in a non-contact manner, a pin is placed on the respective pads which are connected for each circuit portion, and then the supplying of power is performed, or grounding is performed, which results in time-consuming effort being generated in the case of performance in a contact manner. In other words, there occurs a problem that time-consuming effort is required to align a large number of pads and a large number of pins.
Consequently, in Japanese Laid-Open Patent Publication NO. 2005-30877, there has been proposed a semiconductor device 100 as shown in FIG. 15. In this semiconductor device 100, each of the semiconductor chips 104 is connected to interconnects 101 and 102 in a scribe region.
The supplying of power is performed through these interconnects 101 and 102, and grounding is performed through these interconnects 101 and 102, so that placing the pin on the power supply pad of a portion of the semiconductor chip 104 allows power to be supplied.
However, in the semiconductor device 100 disclosed in Japanese Laid-Open Patent Publication NO. 2005-30877, there occurs the following problem.
In this semiconductor device 100, the interconnects 101 and 102 are drawn throughout the scribe region. Therefore, when the dicing of the semiconductor device 100 is performed for each semiconductor chip 104, a large amount of interconnect debris is generated. Such large amounts of debris are attached to the semiconductor chip, thereby having significant influence on the performance of the semiconductor chip.
Typically, a circuit for checking the performance of transistors inside the semiconductor chip, or an alignment mark and the like, is formed in the scribe region. Therefore, as in Japanese Laid-Open Patent Publication NO. 2005-30877, drawing the power supply interconnects throughout the entire scribe region is in practice troublesome.